Today's integrated circuit chips comprise a large number of functions and components which need to be managed. Typically, a dedicated chip hardware component acting as service module and being interoperable with some on-chip sensors and control elements is used for performing said management.
Some management tasks must be executed more urgently than others (e.g. tasks for preventing inconsistent or harmful system states). Two approaches and corresponding chip architectures exist for ensuring that highly urgent tasks are executed quickly: A) chips comprising a single management unit using unconditional interruption of the currently executed task in favor of the urgent task, and B) chips comprising two or more management units, wherein at least one management unit is selectively reserved for performing a low priority task and wherein at least one further management unit is selectively reserved for immediately performing a high priority task if requested.
According to approach A), a chip uses a single management unit for executing chip component management tasks whereby only one task can be executed at a time. In case the execution of an urgent task is necessary, said urgent task is executed by the management unit immediately and any other task which may currently be executed at said moment is terminated abruptly. Such chips are cheap to manufacture but the abrupt interruption of a currently executed task may cause inconsistent system states or may even damage chip components. A graceful termination is not supported by this chip architecture as the option of a graceful termination bears the risk that in case the currently executed task is trapped in an infinite loop, the current task may never terminate gracefully and thus the urgent task may never be executed. In case the urgent task is to prevent damage to a chip component, the incapability to execute the urgent task may cause damage to the chip.
According to approach B), a chip comprises multiple management units. In this architecture, low-priority tasks are selectively assigned to one of said management units while an urgent task may selectively be assigned to another one of the management units. As one management unit is exclusively reserved for an urgent task, it is ensured that the urgent task can be executed immediately. This approach has the disadvantage that the management unit reserved for urgent tasks is idle most of the time. Thus, the available hardware resources are used inefficiently. Moreover, such multi-management-unit-chips are more expensive to manufacture.